1. Field of the Invention
The present invention relates to a circuit assembly including a VLSI package in which a package substrate carries an IC chip on one major surface thereof while a plurality of connection pads are provided on the other major surface thereof in a two-dimensional format.
2. Description of the Related Arts
Recently, the degree of integration of the VLSI has been more enhanced and accordingly the number of the connection pins per one IC package substrate has been much increased. The connection pins are formed on the bottom surface of the IC package substrate in a two-dimensional manner so as to suppress the largeness of the size of the package substrate. An example of such a two-dimensional arrangement of the connection pin is the so-called xe2x80x9cpin grid array (PGA)xe2x80x9d. The PGA technique is so effective in enhancing the degree of integration of a VLSI since such technique can avoid the situation in which the pitch between the connection pins becomes too narrow because of the two-dimensional arrangement of the connection terminals.
However, there is still encountered some constructive restrictions such as restriction in the pitch length and difficulty in providing signal lines between the connection pins when the PGA package is to be mounted on a mother board i.e. a printed circuit board, because of restrictions in the mounting arrangement within the mother board.
Therefore, there have been developed the surface mount type PGA, the land grid array (LGA), etc. In the LGA arrangement, no pin is used, but only pads are provided for electric connections to the mother board thereby to avoid the restriction encountered in the PGA assembly. However, the LGA assembly needs connectors, which causes a substantial increase in the size of the overall assembly, and unreliable electric connections.
In order to solve the above-mentioned problem having occurred in the LGA arrangement, there has developed the so-called ball grid array (BGA). In the BGA assembly, a package substrate carrying an IC chip on one major surface thereof is provided on the other surface thereof with a plurality of solder bumps arranged in a two-dimensional manner. The BGA arrangement is advantageous because of its electric characteristics of low capacitance and low inductance, and is welcomed as a package of a low cost.
FIGS. 1A and 1B are respectively sectional and plan views showing an exemplary arrangement including a VLSI package assembly with the BGA. FIGS. 2A through 2C are sectional views each showing in an enlarged scale an electrical connection assembly provided between a package substrate and a mother board.
Referring now to FIG. 1A, there is shown a BGA package 50 which includes an IC chip 51 connected through a plurality of soldering bumps 52 mounted on one major surface of a package (PKG) substrate 53. The IC chip 51 is embedded within a plastic mold 58. On the other major surface of the PKG substrate 53 are formed a plurality of soldering bumps 55 for PKG I/O connection in such a two-dimensional format as shown in FIG. 1B. These soldering bumps 55 interconnect the PKG I/O pads 54 formed on the PKG substrate 53 and the mother board I/O pads 57 as clearly seen from FIG. 2A.
It is, in this instance, to be noted that the surfaces of the PKG I/O pads 54 and the mother board I/O pads 57 may be independently treated through a treatment process such as the normal (continuous current supplied) or flashing (intermittent current supplied) plating process with gold by the respective parts suppliers.
A soldering resist layer 60 covers the major surface of the PKG substrate 53 confronting the mother board 56 but other than central portions of the respective pads 54. A soldering resist layer 61 covers the major surface of the mother board 56 confronting the PKG substrate 53 but other than the central portions of the respective pads 57. These soldering resist layers 60 and 61 are effective for preventing the PKG I/O connection soldering bump 55 from adhering to the PKG substrate and mother board 56.
FIG. 2C is a plan view of the arrangement of FIG. 2A along a line Axe2x80x94A appearing in FIG. 2A. As seen from FIG. 2C, the mother board I/O pad 57 includes a soldering connection part 57a which is to be connected with the soldering bump 55 and an external connection part 57b. It is now to be understood that a central portion of the soldering connection part 57a is exposed to the outside through an aperture 60a of the soldering resist 61 so that the central portion can be connected with the soldering bump 55.
When it is intended to electrically connect the PKG substrate 53 and the motor board 56, they are so positioned relative to each other that the PKG I/O pads 53 and the mother board I/O pads 57 confront each other, respectively and they are temporarily fastened to each other by an appropriate tool (not shown). Thereafter, the soldering bumps 55 are provided through a process such as reflowing process so as to provide electrical connection between the PKG I/O pads 54 and the mother board I/O pads 57.
It is to be noted that the BGA package is subjected to abrupt temperature changes when the PKG substrate 53 and the mother board 56 are electrically connected to each other through the reflowing process of the soldering bumps 55. Furthermore, the BGA package might be used within an apparatus which is subject to such abrupt temperature changes. When the BGA package is used within such apparatus being subject to abrupt temperature changes, there may arise non-uniform temperature distribution because of heat caused by operation of the BGA package. In such situation, various stresses appear within the bumps 55 because of differences in thermal expansion between the PKG package substrate 53 and the mother board 56 and therefore such a problem arises that some connecting areas or portions between the soldering bumps and the pads are peeled off.
On the other hand, the enhancement of the integration degree of the VLSI causes decrease in size of soldering connection part 57a which is shown in FIG. 2C. Thus, the dimension of the connecting area between the soldering bump 55 and the soldering connection part 57a decreases. When such BGA package with such narrow connection areas at the soldering connections is used in an apparatus, such as a portable device, which is subject to shocks because of dropping, the BGA package might be subject to breakage in the electrical connections between the pads 54 and 57.
As shown in more detail in FIG. 2B, it happens because of the abrupt changes in temperature and/or mechanical shocks that a gap 61 appears between the soldering bump 55 and the pad 57 thereby to destroy the electrical connection therebetween.
It is now apparent that there has been such a problem in a prior art package that electrical disconnection is liable to occur between the pads 54 and 57.
Accordingly, an object of the present invention is to provide a VLSI package assembly which can surely keep the electrical connection between the PKG substrate and the mother board while the connection terminals or pads are arranged in a two-dimensional format.
According to the present invention, an improved VLSI package assembly is provided which comprises a PKG substrate carrying on one major surface thereof an IC chip and having a plurality of first connection pads arranged in a two-dimensional format; a mother board having a plurality of second connection pads two-dimensionally arranged on one surface thereof confronting said other surfaced of the PKG substrate; and connection elements electrically connecting between the first and second connection pads, wherein an electric connecting assembly constituted by said first and second connections pads and said connection elements includes an anti-stress structure with a high durability against stresses occurring therein.
According to one aspect of the present invention, one of the first and second pads has a smaller exposed area for soldering than the other in case said one is treated with an electrolytic plating process but the other is treated with a non-electrolytic plating process. With this arrangement, connection strength at the respective connection of the respective first and second connection pads with the soldering elements is kept substantially uniform. This is based on a finding that the solder can adhere to the surface of the connection pad plated with a metal such as gold through the electrolytic process more strongly than to the surface of the connection pads plated with the same metal through the non-electrolytic process.
According to a second aspect of the present invention, there formed a second connection pad on the major surface of the mother board confronting the major surface of the PKG substrate on which a first connection pad is formed and the second connection pad includes a resilient structure. That is, the second connection pad is not separated from the connection element even though a stress appears in the electric connection assembly because of difference in thermal expansion between the PKG substrate and the mother board since the stress is absorbed by the resilient structure. In other words, the electric connection by means of solder between the first and second connection pads is securely kept.
According to a third aspect of the present invention, the resilient structure is constituted by the first and second connections pads and the connection elements such as a solder piece and the second connection pad includes a resilient flat plate which is divided into two pieces.
According to a fourth aspect of the present invention, the resilient structure is constituted by the first and second connection pads and the connection elements and the second connection pad includes a resilient flat plate which is divided into two pieces which are apart from each other.